© 2003 Fairchild Semiconductor Corporation DS500777 www.fairchildsemi.com
January 2003
Revised January 2003
1
00L
V
E
L
T
22 3.
3V
Dual

L
V
TTL/
L
V
CM
OS to Dif
f
er
enti
al L
VPECL
T
r
ansla
t
or
100LVELT22
3.3V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential
LVPECL translator operating from a single +3.3V supply.
Both outputs of a differential pair should be terminated in
50Ω to V
CC
- 2.0V even if only one output is being used. If
an output pair is unused both outputs can be left open
(un-terminated).
The 100 series is temperature compensated.
Features
a73 Typical propagation delay of 350 ps
a73 <100 ps skew between outputs
a73 Max I
CC
of 28 mA at 25°C
a73 When TTL input is left Open Q output defaults HIGH
a73 Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
a73 Flow through pinout
a73 Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
a73 Moisture Sensitivity Level 1
a73 ESD Performance:
Human Body Model > 2000V
Machine Model > 200V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Package DescriptionPackage Code
Number Top Mark
100LVELT22M M08A KVT22 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100LVELT22M8
(Preliminary)
MA08D KR22 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name Description
Q
n
, Q
n
LVPECL Differential Outputs
D
0
, D
1
LVTTL/LVCMOS Inputs
V
CC
Positive Supply
GND Ground