1. General description
The LVT125 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
2. Features
a73 Quad bus interface
a73 3-state buffers
a73 Output capability: +64 mA and −32 mA
a73 TTL input and output switching levels
a73 Input and output interface capability to systems at 5 V supply
a73 Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
a73 Live insertion and extraction permitted
a73 No bus current loading when output is tied to 5 V bus
a73 Power-up 3-state
a73 Latch-up protection:
a78 JESD78: exceeds 500 mA
a73 ESD protection:
a78 MIL STD 883 method 3015: exceeds 2000 V
a78 Machine model: exceeds 200 V
3. Quick reference data
74LVT125
3.3 V quad buffer; 3-state
Rev. 05 — 10 February 2005 Product data sheet
Table 1: Quick reference data
GND = 0 V; T
amb
=25°C.
Symbol Parameter Conditions Min Typ Max Unit
t
PLH
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V - 2.7 - ns
t
PHL
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V - 2.9 - ns
C
I
input capacitance V
I
= 0 V or 3.0 V - 4 - pF
C
O
output capacitance outputs disabled;
V
O
= 0 V or 3.0 V
-8-pF
I
CC
quiescent supply current outputs disabled;
V
CC
= 3.6 V
- 0.13 - mA