© 2005 Fairchild Semiconductor Corporation DS012411 www.fairchildsemi.com
March 1995
Revised February 2005
7
4LCX08
Low V
o
l
t
age Quad
2-
I
nput AND
Gate wit
h

5
V
T
o
le
rant

I
nput
s
74LCX08
Low Voltage Quad 2-Input AND Gate
with 5V Tolerant Inputs
General Description
The LCX08 contains four 2-input AND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
The 74LVX08 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
a73 5V tolerant inputs
a73 2.3V–3.6V V
CC
specifications provided
a73 5.5 ns t
PD
max (V
CC
c32 3.3V), 10 c80A I
CC
max
a73 Power down high impedance inputs and outputs
a73 c11424 mA output drive (V
CC
c32 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds JEDEC 78 conditions
a73 ESD performance:
Human body model c33 2000V
Machine model c33 150V
a73 Leadless Pb-Free DQFN package

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
Note 2: DQFN package available in Tape and Reel only.
Order Number
Package
Number
Package Description
74LCX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX08MX_NL
(Note 1)
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX08BQX
(Note 2)
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX08MTCX_NL
(Note 1)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide