1
H
A
L
O
G
EN
F
R
E
E
TM
L
E
A
D F R
E
E
CS
SK
DI
DO
V
CC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
V
CC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
V
CC
CS
SK
RESET
GND
DO
DI
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
DO
V
CC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
V
CC
CS
SK
RESET
GND
DO
DI
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
a73 SPI bus compatible
a73 Low power CMOS technology
a73 2.5V to 6.0V operation
a73 Self-timed write cycle with auto-clear
a73 Hardware reset pin
a73 Hardware and software write protection
a73 Commercial, industrial and automotive
temperature ranges
a73 Power-up inadvertant write protection
a73 RDY/BSY pin for end-of-write indication
a73 1,000,000 program/erase cycles
a73 100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W) TSSOP Package (U, Y)
PIN FUNCTIONS
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
V
CC
+2.5V to +6.0V Power Supply
GND Ground
RESET Reset
RDY/BUSY Ready/BUSY Status
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1021, Rev. B
SOIC Package (S, V) TSSOP Package (UR, YR)
64LC10/20/40 F02
V
CC
ADDRESS
DECODER
MEMORY ARRAY
64/128/256 x 16
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
RESET
GND
RDY/BUSY