Publication# 08007 Rev. H Amendment /0
Issue Date: May 1995
2-32
Advanced
Micro
Devices
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS EPROM
FINAL
DISTINCTIVE CHARACTERISTICS
a73 Fast access time
— 55 ns
a73 Low power consumption
— 20 m A typical CMOS standby current
a73 JEDEC-approved pinout
a73 Single +5 V power supply
a73 – 10% power supply tolerance available
a73 100% Flashrite programming
— Typical programming time of 4 seconds
a73 Latch-up protected to 100 mA from –1 V to
VCC + 1 V
a73 High noise immunity
a73 Versatile features for simple interfacing
— Both CMOS and TTL input/output
compatibility
— Two line control functions
a73 Standard 28-pin DIP, PDIP, 32-pin TSOP and
PLCC packages
GENERAL DESCRIPTION
The Am27C256 is a 256K-bit ultraviolet erasable pro-
grammable read-only memory. It is organized as 32K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast sin-
gle address location programming. Products are avail-
able in windowed ceramic DIP packages as well as plas-
tic one time programmable (OTP) PDIP, TSOP, and
PLCC packages.
Typically, any byte can be accessed in less than 55 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C256 offers
separate Output Enable (OE) and Chip Enable (CE)
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 m W in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C256 supports AMD’s Flashrite
programming algorithm (100 m s pulses) resulting in typi-
cal programming time of 4 seconds.
BLOCK DIAGRAM
VCC
VSS
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
CE
OE
Output
Buffers
Y
Gating
262,144
Bit Cell
Matrix
A0–A14
Address
Inputs
Data Outputs
DQ0–DQ7
08007H-1
VPP