74VHCT138A
3 TO 8 LINE DECODER (INVERTING)
PRELIMINARY DATA
March 2000
n HIGH SPEED: tPD = 7.6 ns (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25
o
C
n COMPATIBLEWITH TTL OUTPUTS:
VIH =2V(MIN),VIL = 0.8V(MAX)
n POWERDOWN PROTECTIONON INPUTS &
OUTPUTS
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
n IMPROVED LATCH-UP IMMUNITY
n LOW NOISE: V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHCT138A is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputsgo to high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS

SOP TSSOP
ORDER CODES
PACKAGE TUBE T & R
SOP 74VHCT138AM 74VHCT138AMTR
TSSOP 74VHCT138ATTR
1/8