1/14August 2004
a73 HIGH SPEED:
t
PD
= 5.5ns (TYP.) at V
CC
= 3.3V
a73 5V TOLERANT INPUTS
a73 INPUT VOLTAGE LEVEL:
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
a73 LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 594
a73 IMPROVED LATCH-UP IMMUNITY
a73 POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX594 is a low voltage CMOS 8 BIT
SHIFT REGISTER WITH OUTPUT REGISTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power, battery operated and low
noise 3.3V applications.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding
clear (SCLR, RCLR) are provided for both the shift
register and the storage register. A serial (QH’)
output is provided for cascading purposes. Both
the shift register and storage register use
positive-edge triggered clocks. If the clocks are
connected together, the shift register state will
always be one clock pulse ahead of the storage
register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V system. It combines
high speed performance with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX594
LOW VOLTAGE CMOS 8 BIT SHIFT REGISTER
WITH OUTPUT REGISTER (5V TOLERANT INPUTS)

Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX594MTR
TSSOP 74LVX594TTR
TSSOPSOP
Rev. 5