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Preliminary Technical Data ADSP-2188M
DSP
Microcomputer
This information applies to a product under development. Its characteristics and
specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacturing unless otherwise agreed to in writing.
One Technology Way http://www.analog.com/dsp
P.O. Box 9106 Tel: 1-800-ANALOG-D
Norwood MA 02062-9106 Fax: 1-781-461-3010
U.S.A. Analog Devices Inc., 1999
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FEATURES
Performance
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12.5 ns Instruction Cycle Time @ 2.5 Volts (internal), 75 MIPS Sustained Performance
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Single-Cycle Instruction Execution
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Single-Cycle Context Switch
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3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
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Multifunction Instructions
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Powerdown Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from
Powerdown Condition
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Low Power Dissipation in Idle Mode
Integration
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ADSP-2100 Family Code Compatible (easy to use algebraic syntax), with Instruction Set Extensions
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256K Bytes of On-Chip RAM, Configured as 48K Words On-Chip Program Memory RAM and 56K Words
On-Chip Data Memory RAM
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Dual Purpose Program Memory for Both Instruction and Data Storage
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Independent ALU, Multiplier/Accumulator, & Barrel Shifter Computational Units
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Two Independent Data Address Generators
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Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution
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Programmable 16-Bit Interval Timer with Prescaler
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100-Lead LQFP
System Interface
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Flexible I/O structure allows 2.5V or 3.3V operation; all inputs tolerate up to 3.6V regardless of mode
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16-Bit Internal DMA Port for High Speed Access to on-Chip Memory (Mode Selectable)
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4 MByte Memory Interface for Storage of Data Tables & Program Overlays (Mode Selectable)
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8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable)
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I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable)
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Programmable Memory Strobe & Separate I/O Memory Space Permits “Glueless” System Design
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Programmable Wait State Generation
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Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering
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Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
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Six External Interrupts
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13 Programmable Flag Pins Provide Flexible System Signaling
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UART Emulation through Software SPORT Reconfiguration
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ICE-Port™ Emulator Interface Supports Debugging in Final Systems