TL/F/11613
74LVX373
Low
Voltage
Octal
Transparent
Latch
with
TRI-STATE
Outputs
January 1996
74LVX373
Low Voltage Octal Transparent Latch
with TRI-STATE Outputs
General Description
The LVX373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The latches ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state. The inputs tolerate up
to 7V allowing interface of 5V systems to 3V systems.
Features
Y
Input voltage translation from 5V to 3V
Y
Ideal for low power/low noise 3.3V applications
Y
Available in SOIC JEDEC, SOIC EIAJ and TSSOP
packages
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Logic Symbols Connection Diagram
TL/F/11613–1
IEEE/IEC
TL/F/11613–4
Pin Assignment for
SOIC and TSSOP
TL/F/11613–2
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE Output Enable Input
O
0
–O
7
TRI-STATE Latch Outputs
SOIC JEDEC SOIC EIAJ TSSOP
Order Number 74LVX373M 74LVX373SJ 74LVX373MTC
74LVX373MX 74LVX373SJX 74LVX373MTCX
See NS Package Number M20B M20D MTC20
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A. http://www.national.com