ATV5000
器件描述：High Density UV Erasable Programmable Logic Device
器件厂商：ATMEL [ATMEL Corporation]
文件大小：156.88KB，共13页
Sponsor by e络盟器件资料摘要：
Features
•
Advanced Programmable Logic Device - High Gate Utilization
•
Flexible Interconnect Architecture - Universal Routing
•
Flexible Logic Cells - 128 Flip-Flops and 52 Latches
•
Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
•
High Speed - 50 MHz Operation
•
Complete Third Party Software Support
No Placement, Routing or Layout Software Required
•
Proven and Reliable High Speed CMOS EPROM Process
2000 V ESD Protection
200 mA Latchup Immunity
•
Reprogrammable - Tested 100% for Programmability
•
Commercial, Industrial and Military Temperature Grades
UNIVERSAL
AND
REGIONAL
INTERCONNECT
52 INPUT
LATCHES
52 LOGIC CELLS
(104 FLIP-FLOPS)
24 BURIED CELLS
(24 FLIP-FLOPS)
8
INPUT
PINS
52
I/O
PINS
Block Diagram
Chip Carrier
Pin Configuration
Pin Name Function
IN Logic and Clock Inputs
Pins 2,32,36,66 Input/Register Clocks 1-4
Pins 1,34,35,68 Input/Latch Clocks 1-4
I/O Bidirectional Buffers
VCC +5 V Supply
High Density
UV Erasable
Programmable
Logic Device
Description
The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu-
lar architecture translates into increased utilization and high performance.
The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter-
connection of and uniform performance from all nodes. "Sum terms", which are easy to use
groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire-
OR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms
feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term.
Each I/O pin has an individually enabled input latch.
All 128 registers are configurable as D- or T-types without using extra logic gates. Individual
sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A
direct "clock from pin" option guarantees synchronization and fast clock to output perform-
ance.
Standard, off-the-shelf third-party software tools and programmers support the ATV5000.
This minimizes start-up investment and improves product support.
I/Os
GND
I/Os
VCC
I/Os
I/Os
VCC
I/Os
GND
I/Os
18
52
35
1
I/Os I/Os
VCC GND
IN
IN
GND VCC
INI/Os I/OsIN
JLCC
0065B
ATV5000/L
1-193
•
Advanced Programmable Logic Device - High Gate Utilization
•
Flexible Interconnect Architecture - Universal Routing
•
Flexible Logic Cells - 128 Flip-Flops and 52 Latches
•
Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
•
High Speed - 50 MHz Operation
•
Complete Third Party Software Support
No Placement, Routing or Layout Software Required
•
Proven and Reliable High Speed CMOS EPROM Process
2000 V ESD Protection
200 mA Latchup Immunity
•
Reprogrammable - Tested 100% for Programmability
•
Commercial, Industrial and Military Temperature Grades
UNIVERSAL
AND
REGIONAL
INTERCONNECT
52 INPUT
LATCHES
52 LOGIC CELLS
(104 FLIP-FLOPS)
24 BURIED CELLS
(24 FLIP-FLOPS)
8
INPUT
PINS
52
I/O
PINS
Block Diagram
Chip Carrier
Pin Configuration
Pin Name Function
IN Logic and Clock Inputs
Pins 2,32,36,66 Input/Register Clocks 1-4
Pins 1,34,35,68 Input/Latch Clocks 1-4
I/O Bidirectional Buffers
VCC +5 V Supply
High Density
UV Erasable
Programmable
Logic Device
Description
The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu-
lar architecture translates into increased utilization and high performance.
The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter-
connection of and uniform performance from all nodes. "Sum terms", which are easy to use
groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire-
OR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms
feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term.
Each I/O pin has an individually enabled input latch.
All 128 registers are configurable as D- or T-types without using extra logic gates. Individual
sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A
direct "clock from pin" option guarantees synchronization and fast clock to output perform-
ance.
Standard, off-the-shelf third-party software tools and programmers support the ATV5000.
This minimizes start-up investment and improves product support.
I/Os
GND
I/Os
VCC
I/Os
I/Os
VCC
I/Os
GND
I/Os
18
52
35
1
I/Os I/Os
VCC GND
IN
IN
GND VCC
INI/Os I/OsIN
JLCC
0065B
ATV5000/L
1-193