5390A–BDC–06/04
Dual 8-bit
500 Msps ADC
AT84AD004
Smart ADC

Features
Dual ADC with 8-bit Resolution
500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode
Single or 1:2 Demultiplexed Output
LVDS Output Format (100Ω)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
LQFP144 Package
Temperature Range:
– 0°C < T
A
< 70°C (Commercial Grade)
– -40°C < T
A
< 85°C (Industrial Grade)
3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Performance
Low Power Consumption: 0.7W per Channel
Power Consumption in Standby Mode: 120 mW
1 GHz Full Power Input Bandwidth (-3 dB)
SNR = 43 dB Typ (7.0 ENOB), THD = -53 dBc, SFDR = -55 dBc at Fs = 500 Msps
Fin = 250 MHz
2-tone IMD3: -54 dBc (249 MHz, 251 MHz) at 500 Msps
DNL = 0.25 LSB, INL = 0.5 LSB
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
Low Bit Error Rate (10
-15
) at 500 Msps
Application
Instrumentation
Satellite Receivers
Direct RF Down Conversion
WLAN
1