AX88195P
器件资料摘要：
ASIX ELECTRONICS CORPORATION First Released Date : Oct/02/1998
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88195P
10/100BASE Fast Ethernet MAC Controller
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
Document No.: AX195-17 / V1.7 / May. 12 ’ 00
Features
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
• NE2000 register level compatible instruction
• Support both 8 bit and 16 bit local CPU interf ace s
include MCS-51 series, 80186 series and MC68K
series CPU
• Support both 10Mbps and 100Mbps data rate
• Support both full-duplex or half-duplex operation
• Provides a MII port for both 10/100Mbps operation
• Support EEPROM interface to store MAC address
• External and internal loop-back capability
• Two external 32K*8 Asynchronous SRAMs
required for packet buffer
• 128-pin LQFP low profile package
• 2 5MHz Operation, Dual 5V and 3.3 V CMOS
process with 5V I/O tolerance . Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88195 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller.
The AX88195 supports both 8 bit and 16 bit local CPU interf ace s include MCS-51 series, 80x86 series, MC68K series
CPU and ISA bus. The AX88195 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify the
design. Two low cost 32k*8 SRAM is required for packet buffer.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
CPU LATCH
AX88195
AD BUS
Addr L
Addr H
Ctl BUS
BUFFER
SRAM
PHY/TxRx RJ45
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88195P
10/100BASE Fast Ethernet MAC Controller
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
Document No.: AX195-17 / V1.7 / May. 12 ’ 00
Features
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
• NE2000 register level compatible instruction
• Support both 8 bit and 16 bit local CPU interf ace s
include MCS-51 series, 80186 series and MC68K
series CPU
• Support both 10Mbps and 100Mbps data rate
• Support both full-duplex or half-duplex operation
• Provides a MII port for both 10/100Mbps operation
• Support EEPROM interface to store MAC address
• External and internal loop-back capability
• Two external 32K*8 Asynchronous SRAMs
required for packet buffer
• 128-pin LQFP low profile package
• 2 5MHz Operation, Dual 5V and 3.3 V CMOS
process with 5V I/O tolerance . Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88195 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller.
The AX88195 supports both 8 bit and 16 bit local CPU interf ace s include MCS-51 series, 80x86 series, MC68K series
CPU and ISA bus. The AX88195 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify the
design. Two low cost 32k*8 SRAM is required for packet buffer.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
CPU LATCH
AX88195
AD BUS
Addr L
Addr H
Ctl BUS
BUFFER
SRAM
PHY/TxRx RJ45