DSP56F801/D
Rev. 13.0, 02/2004
© Motorola, Inc., 2004. All rights reserved.
56F801
Technical Data
56F801 16-bit Hybrid Controller
• Up to 30 MIPS operation at 60MHz core
frequency
Up to 40 MIPS operation at 80MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
Hardware DO and REP loops
6-channel PWM Module
Two 4-channel, 12-bit ADCs
Serial Communications Interface (SCI)
8K × 16-bit words Program Flash
1K × 16-bit words Program RAM
2K × 16-bit words Data Flash
1K × 16-bit words Data RAM
2K × 16-bit words Boot Flash
Serial Peripheral Interface (SPI)
General Purpose Quad Timer
JTAG/OnCE
TM
port for debugging
On-chip relaxation oscillator
11 shared GPIO
48-pin LQFP Package
Figure 1. 56F801 Block Diagram
JTAG/
OnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
GPIOB3/XTAL
GPIOB2/EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQA
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
or GPIO
Quad Timer C
A/D1
A/D2 ADC
4
2
3
4
4
6
PWM Outputs
Fault Input
PWMA
16 16
VCAPC V
DD
V
SS
V
DDA
V
SSA
6
24 5*
•
•
•
•
•
•
•
•
VREF
*includes TCS pin which is reserved for factory use and is tied to VSS


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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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