54ACT11010, 74ACT11010
TRIPLE 3-INPUT POSITIVE-NAND GATES

SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright  1993, Texas Instruments Incorporated
2–1
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
• EPICC0116 (Enhanced-Performance Implanted
CMOS) 1-C0109m Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain three independent 3-input
NAND gates. They perform the Boolean functions
Y = AC0083BC0083C or Y = A + B + C in positive logic.
The 54ACT11010 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The 74ACT11010 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B C
Y
H H H L
L XX H
X LX H
X X L H
logic symbol
†
7
8
9
10
11
14
15
16
1
3C
3B
3A
2C
2B
2A
1C
1B
1A
3Y
2Y
1Y
6
3
2
&
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
54ACT11010 . . . J PACKAGE
74ACT11010 ...D OR N PACKAGE
logic diagram (positive logic)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
2Y
GND
GND
3Y
3C
3B
1B
1C
2A
V
CC
V
CC
2B
2C
3A
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2C
3A
NC
3B
3C
1C
1B
NC
1A
1Y
54ACT11010 . . . FK PACKAGE
(TOP VIEW)
2A NC
3Y
2B
2Y
GND
NC
NC – No internal connection
GND
1Y
1A
1B
2Y
1C
2A
2B
2C
3Y
3A
3B
3C
V
CC
V
CC
2
3
6
1
16
15
14
11
10
9
8
7
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.