ATTINY22L
器件描述：8-bit Microcontroller with 2K Bytes of In-System Programmable Flash
器件厂商：ATMEL [ATMEL Corporation]
文件大小：252KB，共11页
Sponsor by e络盟器件资料摘要：
1
Features
• Utilizes the AVR
®
RISC Architecture
AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 1MIPS Throughput at 1MHz
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of internal SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– On-chip RC Oscillator
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 3V, 25°C
– Active: 1.5 mA
– Idle Mode: 100 µA
– Power Down Mode: <1 µA
I/O and Packages
– 5 Programmable I/O Lines
– 8-pin PDIP and SOIC
Operating Voltages
– 2.7 - 6.0V
Speed Grade
– Internal Oscillator ~1MHz @ 5.0V
Description
The ATtiny22L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny22L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
Rev. 1273BS–02/00
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
ATtiny22L
Preliminary
Pin Configuration
PDIP/SOIC
1
2
3
4
8
7
6
5
RESET
PB3
PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
Note: This is a summary document. For the complete 56-page
document, please visit our web site at www.atmel.com or e-mail at
literature@atmel.com and request literature #1273B.
Features
• Utilizes the AVR
®
RISC Architecture
AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 1MIPS Throughput at 1MHz
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of internal SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– On-chip RC Oscillator
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 3V, 25°C
– Active: 1.5 mA
– Idle Mode: 100 µA
– Power Down Mode: <1 µA
I/O and Packages
– 5 Programmable I/O Lines
– 8-pin PDIP and SOIC
Operating Voltages
– 2.7 - 6.0V
Speed Grade
– Internal Oscillator ~1MHz @ 5.0V
Description
The ATtiny22L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny22L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
Rev. 1273BS–02/00
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
ATtiny22L
Preliminary
Pin Configuration
PDIP/SOIC
1
2
3
4
8
7
6
5
RESET
PB3
PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
Note: This is a summary document. For the complete 56-page
document, please visit our web site at www.atmel.com or e-mail at
literature@atmel.com and request literature #1273B.