Preliminary Rev. 0.4 5/06 Copyright © 2006 by Silicon Laboratories Si534
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si534
CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
Applications
Description
The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si534
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si534 uses one fixed crystal to
provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si534 IC-based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Functional Block Diagram
null Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
null Four selectable output frequencies
null 3rd generation DSPLL
®
with superior
jitter performance
null 3x better frequency stability than
SAW-based oscillators
null Internal fixed crystal frequency
ensures high reliability and low
aging
null Available CMOS, LVPECL,
LVDS, and CML outputs
null 3.3, 2.5, and 1.8 V supply options
null Industry-standard 5 x 7 mm
package and pinout
null Pb-free/RoHS-compliant
null SONET/SDH
null Networking
null SD/HD video
null Clock and data recovery
null FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®

Clock
Synthesis

V
DD
CLK+CLK–
OE GND
FS[1] FS[0]
Ordering Information:
See page 6.
Pin Assignments:
See page 5.
(Top View)
Si5602
(LVDS/LVPECL/CML)
(CMOS)
1
2
3
6
5
4GND
OE
V
DD
CLK+
CLK–
NC
FS[1]
FS[0]
7
8
1
2
3
6
5
4GND
OE
V
DD
CLK
NC
NC
FS[1]
FS[0]
7
8
PRELIMINARY DATA SHEET