Preliminary Rev. 0.3 4/06 Copyright © 2006 by Silicon Laboratories Si550
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si550
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
Applications
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXO’s where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Functional Block Diagram
null Available with any-rate output
frequencies from 10 MHz to
945 MHz and selected frequencies
to 1.4 GHz
null 3rd generation DSPLL
®
with
superior jitter performance
null 3x better frequency stability than
SAW based oscillators
null Internal fixed crystal frequency
ensures high reliability and low
aging
null Available CMOS, LVPECL,
LVDS, & CML outputs
null 3.3, 2.5, and 1.8 V supply options
null Industry-standard 5 x 7 mm
package and pinout
null Lead-free/RoHS-compliant
null SONET / SDH
null xDSL
null 10 GbE LAN / WAN
null Low-jitter clock generation
null Optical modules
null Clock and data recovery
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
®
Clock Synthesis

ADC
VDD CLK+CLK–
Vc OE GND
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
Si5602
1
2
3
6
5
4
V
C
GND
OE
V
DD
CLK+
CLK–
PRELIMINARY DATA SHEET