1. General description
The 74AUP2G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP2G04 provides two inverting buffers.
2. Features
a73 Wide supply voltage range from 0.8 V to 3.6 V
a73 High noise immunity
a73 Complies with JEDEC standards:
a78 JESD8-12 (0.8 V to 1.3 V)
a78 JESD8-11 (0.9 V to 1.65 V)
a78 JESD8-7 (1.2 V to 1.95 V)
a78 JESD8-5 (1.8 V to 2.7 V)
a78 JESD8-B (2.7 V to 3.6 V)
a73 ESD protection:
a78 HBM JESD22-A114-C Class 3A. Exceeds 5000 V
a78 MM JESD22-A115-A exceeds 200 V
a78 CDM JESD22-C101-C exceeds 1000 V
a73 Low static power consumption; I
CC
= 0.9 µA (maximum)
a73 Latch-up performance exceeds 100 mA per JESD 78 Class II
a73 Inputs accept voltages up to 3.6 V
a73 Low noise overshoot and undershoot < 10 % of V
CC
a73 I
OFF
circuitry provides partial Power-down mode operation
a73 Multiple package options
a73 Specified from −40 °Cto+85°C and −40 °C to +125 °C
74AUP2G04
Low-power dual inverter
Rev. 01. — 16 January 2006 Preliminary data sheet