AZ100LVEL16VR
器件资料摘要：
AZ100LVEL16VR
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• High Bandwidth for ≥1GHz
• Similar Operation as AZ100EL16VO
• Operating Range of 3.0V to 5.5V
• Minimizes External Components
• Selectable Enable Polarity and Threshold
(CMOS/TTL or PECL)
• Available in a 3x3mm MLP Package
DESCRIPTION
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable.
The Q
HG
/Q¯
HG
outputs have a voltage gain several times greater than the Q/Q¯ outputs.
The AZ100LVEL16VR provides a selectable enable that allows continuous oscillator operation. See truth table
below for enable function. If Enable pull-up is desired in the CMOS mode, an external ≤20kΩ resistor connecting
EN to V
CC
will override the on-chip pull-down resistor. The AZ100LVEL16VR also provides a V
BB
and 470Ω
internal bias resistors from D to V
BB
and D¯ to V
BB
. The V
BB
pin can support 1.5mA sink/source current. Bypassing
V
BB
to ground with a 0.01 µF capacitor is recommended.
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See truth table below for current source
functions. External resistors may also be used to increase pull-down current to a maximum total of 25mA.
Outputs Q
HG
/Q¯
HG
each have an optional on-chip pull-down current source of 10mA. When pad/pin V
EEP
is left
open (NC), the output current sources are disabled and the Q
HG
/Q¯
HG
operate as standard PECL/ECL. When V
EEP
is
connected to V
EE
, the current sources are activated. The Q
HG
/Q¯
HG
pull-down current can be decreased, by using a
resistor to connect from V
EEP
to V
EE
.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
MLP 16 AZ100LVEL16VRL AZM16R
MLP 16 T&R AZ100LVEL16VRLR1 AZM16R
MLP 16 T&R AZ100LVEL16VRLR2 AZM16R
DIE AZ100LVEL16VRX N/A
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• High Bandwidth for ≥1GHz
• Similar Operation as AZ100EL16VO
• Operating Range of 3.0V to 5.5V
• Minimizes External Components
• Selectable Enable Polarity and Threshold
(CMOS/TTL or PECL)
• Available in a 3x3mm MLP Package
DESCRIPTION
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable.
The Q
HG
/Q¯
HG
outputs have a voltage gain several times greater than the Q/Q¯ outputs.
The AZ100LVEL16VR provides a selectable enable that allows continuous oscillator operation. See truth table
below for enable function. If Enable pull-up is desired in the CMOS mode, an external ≤20kΩ resistor connecting
EN to V
CC
will override the on-chip pull-down resistor. The AZ100LVEL16VR also provides a V
BB
and 470Ω
internal bias resistors from D to V
BB
and D¯ to V
BB
. The V
BB
pin can support 1.5mA sink/source current. Bypassing
V
BB
to ground with a 0.01 µF capacitor is recommended.
Outputs Q/Q¯ each have a selectable on-chip pull-down current source. See truth table below for current source
functions. External resistors may also be used to increase pull-down current to a maximum total of 25mA.
Outputs Q
HG
/Q¯
HG
each have an optional on-chip pull-down current source of 10mA. When pad/pin V
EEP
is left
open (NC), the output current sources are disabled and the Q
HG
/Q¯
HG
operate as standard PECL/ECL. When V
EEP
is
connected to V
EE
, the current sources are activated. The Q
HG
/Q¯
HG
pull-down current can be decreased, by using a
resistor to connect from V
EEP
to V
EE
.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
MLP 16 AZ100LVEL16VRL AZM16R
MLP 16 T&R AZ100LVEL16VRLR1 AZM16R
MLP 16 T&R AZ100LVEL16VRLR2 AZM16R
DIE AZ100LVEL16VRX N/A