TL/F/10146
54FCT/74FCT273
Octal
D
Flip-Flop
March 1993
54FCT/74FCT273
Octal D Flip-Flop
General Description
The ’FCT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
Features
Y
I
CC
reduced to 40.0 mA
Y
Ideal buffer for MOS microprocessor or memory
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
Buffered, asynchronous master reset
Y
TTL input and output level compatible
Y
TTL levels accept CMOS levels
Y
I
OL
e 48 mA (Com), 32 mA (Mil)
Y
NSC 54/74FCT273 is pin and functionally equivalent to
IDT 54/74FCT273
Y
Military product compliant to MIL-STD-883 and
Standard Military Drawing 5962-87656
Logic Symbols Connection Diagrams
TL/F/10146–1
IEEE/IEC
TL/F/10146–2
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/10146–3
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
Pin Assignment
for LCC
TL/F/10146–4
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.