© 2005 Fairchild Semiconductor Corporation DS500028 www.fairchildsemi.com
January 1998
Revised April 2005
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74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a Latch Enable input (LE) and an Out-
put Enable input (OE). When the OE input is HIGH, the
eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
a73 High speed: t
PD
c32 7.7 ns (typ) at T
A
c32 25c113C
a73 High Noise Immunity: V
IH
c32 2.0V, V
IL
c32 0.8V
a73 Power Down Protection is provided on all inputs and
outputs
a73 Low Noise: V
OLP
c32 1.6V (max)
a73 Low Power Dissipation:
I
CC
c32 4 c80A (max) @ T
A
c32 25c113C
a73 Pin and function compatible with 74HCT573

Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74VHCT573AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHCT573ASJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT573AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT573AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide