74AC163MTC
器件描述：Synchronous Presettable Binary Counter
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：112.08KB，共11页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS009932 www.fairchildsemi.com
November 1988
Revised February 2000
74
A
C
16
3
• 74ACT163 Synchronous
Pre
sett
able
Bi
nary Counter
74AC163 • 74ACT163
Synchronous Presettable Binary Counter
General Description
The AC/ACT163 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
Features
a73 I
CC
reduced by 50%
a73 Synchronous counting and loading
a73 High-speed synchronous expansion
a73 Typical count rate of 125 MHz
a73 Outputs source/sink 24 mA
a73 ACT163 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
SR Synchronous Reset Input
P
0
–P
3
Parallel Data Inputs
PE Parallel Enable Input
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output
November 1988
Revised February 2000
74
A
C
16
3
• 74ACT163 Synchronous
Pre
sett
able
Bi
nary Counter
74AC163 • 74ACT163
Synchronous Presettable Binary Counter
General Description
The AC/ACT163 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
Features
a73 I
CC
reduced by 50%
a73 Synchronous counting and loading
a73 High-speed synchronous expansion
a73 Typical count rate of 125 MHz
a73 Outputs source/sink 24 mA
a73 ACT163 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
SR Synchronous Reset Input
P
0
–P
3
Parallel Data Inputs
PE Parallel Enable Input
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output