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ADSP-21mod870
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Internet Gateway Processor
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORTS
SPORT 1SPORT 0
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
BYTE DMA
CONTROLLER
16K324 PM
8K324 OVERLAY 1
8K324 OVERLAY 2
TIMER
ADSP-2100 BASE
ARCHITECTURE
SHIFTERMACALU
ARITHMETIC UNITS
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2DAG 1
DATA ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUS
INTERNAL
DMA
PORT
EXTERNAL
DATA
BUS
OR
FULL MEMORY
MODE
HOST MODE
16K316 DM
8K316 OVERLAY 1
8K316 OVERLAY 2
FEATURES
PERFORMANCE
Complete Single-Chip Internet Gateway Processor (No
External Memory Required)
Implements V.34/V.90 Data/FAX Modem Including
Controller and Datapump
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained
Performance
Open Architecture Platform Extensible to Voice Over IP
and Other Applications
Low Power Dissipation, 80 mW (Typical) for Digital
Modem
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
On-Chip Program Memory RAM and 32K Words On-
Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP with 0.4 Square Inch (256 mm
2
) Footprint
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to On-
Chip Memory (Mode Selectable)
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable Multichannel Serial Port Supports
24/32 Channels
Automatic Booting of On-Chip Program Memory
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
GENERAL DESCRIPTION
The ADSP-21mod870 is a single-chip Internet gateway pro-
cessor optimized for implementation of a complete V.34/56K
modem. All data pump and controller functions can be imple-
mented on a single chip, offering the lowest power consumption
and highest possible modem port density.
The ADSP-21mod870, shown in the Functional Block Dia-
gram, combines the ADSP-2100 family base architecture (three
computational units, data address generators and a program
sequencer) with two serial ports, a 16-bit internal DMA port, a
byte DMA port, a programmable timer, Flag I/O, extensive
interrupt capabilities and on-chip program and data memory.
The ADSP-21mod870 integrates 160K bytes of on-chip
memory configured as 32K words (24-bit) of program RAM,
and 32K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-21mod870 is available in
100-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21mod870 operates with a 19 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-21mod870’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-21mod870
can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
ICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.