74VHCT125A
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA

August 1999
PIN CONNECTION AND IEC LOGIC SYMBOLS
n HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
I
CC
=4 µA (MAX.) at T
A
=25
o
C
n COMPATIBLEWITH TTL OUTPUTS:
VIH =2V(MIN),VIL = 0.8V(MAX)
n POWERDOWN PROTECTIONON INPUTS &
OUTPUTS
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
n IMPROVED LATCH-UP IMMUNITY
n LOW NOISE: VOLP = 0.8V(Max.)
DESCRIPTION
The 74VHCT125A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
ORDER CODES :
74VHCT125AM 74VHCT125AT
M
(Micro Package)
T
(TSSOP Package)
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