C0098C0113C0050C0050C0048C0053C0076C0089

SLUS581 − FEBRUARY 2004
C0080C0079C0087C0069C0082 C0077C0079C0078C0073C0084C0079C0082C0073C0078C0071 C0065C0078C0068 C0083C0087C0073C0084C0067C0072C0073C0078C0071 C0067C0079C0078C0084C0082C0079C0076C0076C0069C0082
C0070C0079C0082 C0051C0046C0051C0262C0086 C0083C0082C0065C0077
1
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FEATURES
C0068 Power Monitoring and Switching for
Non-Volatile Control of SRAMs
C0068 Input Decoder Allows Control of 1 or 2 Banks
of SRAM
C0068 Write-Protect Control
C0068 3-V Primary Cell Input
C0068 3.3-V Operation
C0068 Reset Output for System Power-On Reset
C0068 Less than 20-ns Chip Enable Propagation
Delay
C0068 Small 16-Lead TSSOP Package
APPLICATIONS
C0068 NVSRAM Modules
C0068 Point-of-Sale Systems
C0068 Facsimile, Printers and Photocopiers
C0068 Internet Appliances
C0068 Servers
C0068 Medical Instrumentation and Industrial
Products

DESCRIPTION
The CMOS bq2205 SRAM non-volatile controller
with reset provides all the necessary functions for
converting one or two banks of standard CMOS
SRAM into non-volatile read/write memory.
A precision comparator monitors the 3.3-V VCC
input for an out-of-tolerance condition. When
out-of-tolerance is detected, the two conditioned
chip-enable outputs are forced inactive to
write-protect both banks of SRAM.
Power for the external SRAMs, VOUT, is switched
from the VCC supply to the battery-backup supply
as VCC decays. On a subsequent power-up, the
VOUT supply is automatically switched from the
backup supply to the VCC supply. The external
SRAMs are write-protected until a power-valid
condition exists. The reset output provides
power-fail and power-on resets for the system.
During power-valid operation, the input decoder, A,
selects one of two banks of SRAM.
UDG−03129
V
CC
V
SS
RST
CE
CON2
CE
CON1
V
CC
V
CC
CE
CE
CE
12
1
4
13
10
VOUT
VCC
A
bq2205LYPW
11
9
14
16
VCC
SRAM Bank 2
VCC
SRAM Bank 1
To Microprocessor15
VDC
GND
Backup Supply
VDC
GND
Main Supply
5
8
Pushbutton
Reset
(Optional)
BW
V
SS
V
SS
BC
P
From Address
Selector
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046
C0080C0114C0111C0100C0117C0099C0116C0115 C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115
C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046 C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101
C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
Copyright  2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.