FEATURES
C0068 Maximum Sample Rate: 40MSPS
C0068 12-Bit Resolution
C0068 No Missing Codes
C0068 Power Dissipation: 907mW
C0068 CMOS Technology
C0068 Simultaneous Sample-and-Hold
C0068 70.5dB SNR at 10MHz IF
C0068 Internal and External References
C0068 3.3V Digital/Analog Supply
C0068 Serialized LVDS Outputs
C0068 Integrated Frame and Synch Patterns
C0068 MSB and LSB First Modes
C0068 Option to Double LVDS Clock Output Currents
C0068 Pin- and Format-Compatible Family
C0068 TQFP-80 PowerPAD Package
APPLICATIONS
C0068 Portable Ultrasound Systems
C0068 Tape Drives
C0068 Test Equipment
C0068 Optical Networking
DESCRIPTION
The ADS5270 is a high-performance, 40MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5270 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a PowerPAD TQFP-80 package and
is specified over a −40°C to +85°C operating range.
12−Bit
ADC
PLL
S/H Serializer
1X ADCLK
6X ADCLK
IN1
P
ADCLK
IN1
N
OUT1
P
OUT1
N
12−Bit
ADC
S/H Serializer
IN2
P
IN2
N
OUT2
P
OUT2
N
12−Bit
ADC
S/H Serializer
IN3
P
IN3
N
OUT3
P
OUT3
N
LCLK
P
LCLK
N
ADCLK
P
ADCLK
N
12−Bit
ADC
S/H Serializer
IN4
P
IN4
N
OUT4
P
OUT4
N
12−Bit
ADC
S/H Serializer
IN5
P
IN5
N
OUT5
P
OUT5
N
12−Bit
ADC
S/H Serializer
IN6
P
IN6
N
OUT6
P
OUT6
N
12−Bit
ADC
S/H Serializer
IN7
P
IN7
N
OUT7
P
OUT7
N
12−Bit
ADC
S/H Serializer
Reference
IN8
P
IN8
N
RE
F
T
INT/EXT
V
CM
RE
F
B
OUT8
P
OUT8
N
Registers
SC
L
K
SD
AT
A
CS
Control
R
ESET
PD
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
8-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
C0080C0082C0079C0068C0085C0067C0084C0073C0079C0078 C0068C0065C0084C0065 C0105C0110C0102C0111C0114C0109C0097C0116C0105C0111C0110 C0105C0115 C0099C0117C0114C0114C0101C0110C0116 C0097C0115 C0111C0102 C0112C0117C0098C0108C0105C0099C0097C0116C0105C0111C0110 C0100C0097C0116C0101C0046 C0080C0114C0111C0100C0117C0099C0116C0115
C0099C0111C0110C0102C0111C0114C0109 C0116C0111 C0115C0112C0101C0099C0105C0102C0105C0099C0097C0116C0105C0111C0110C0115 C0112C0101C0114 C0116C0104C0101 C0116C0101C0114C0109C0115 C0111C0102 C0084C0101C0120C0097C0115 C0073C0110C0115C0116C0114C0117C0109C0101C0110C0116C0115 C0115C0116C0097C0110C0100C0097C0114C0100 C0119C0097C0114C0114C0097C0110C0116C0121C0046
C0080C0114C0111C0100C0117C0099C0116C0105C0111C0110 C0112C0114C0111C0099C0101C0115C0115C0105C0110C0103 C0100C0111C0101C0115 C0110C0111C0116 C0110C0101C0099C0101C0115C0115C0097C0114C0105C0108C0121 C0105C0110C0099C0108C0117C0100C0101 C0116C0101C0115C0116C0105C0110C0103 C0111C0102 C0097C0108C0108 C0112C0097C0114C0097C0109C0101C0116C0101C0114C0115C0046
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Copyright  2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.